DM74LSAN Synchronous 4-Bit Binary Counter With Asynchronous Clear. These synchronous, presettable counters feature an internal carry look-ahead for . DM74LSAN datasheet, DM74LSAN circuit, DM74LSAN data sheet: NSC – Synchronous 4-Bit Binary Counters,alldatasheet, datasheet, Datasheet. DM74LSAN datasheet, DM74LSAN circuit, DM74LSAN data sheet: FAIRCHILD – Synchronous 4-Bit Binary Counters,alldatasheet, datasheet.

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The function of the counter whether enabled, datasheeet abled, loading, or counting will be dictated solely by the conditions meeting the stable set-up and hold times.

This synchronous clear allows the count length to be modified easily, as decoding the maximum count desired can be accomplished with one external NAND gate.

Typical power dissipation 93 mW. A buffered clock input triggers the four flip-flops on the rising positive-going edge of the clock input waveform. Vary PRR to measure f. Clock Frequency Note 2. Internal look-ahead for fast counting. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. Typical propagation time, clock to Q output 14 ns. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output.


Changes made to control inputs enable P or T or load that will modify the operating mode have dmm74ls161an effect until clocking occurs. Operating Free Datqsheet Temperature Range. Carry output for n-bit cascading. These counters feature a fully independent clock circuit. sm74ls161an

Index of /datasheet

The device should not be operated at these limits. The clear function for the DM74LSA is synchronous; and a low level at the clear inputs sets all four of the flip-flop outputs LOW after the next clock pulse, regardless of the levels of the enable inputs.

Search field Part name Part description. Free Air Operating Temperature. Enable P and enable T setup times are measured at t. Clear Release Time Note 2. The gate output is connected to the clear input to synchronously clear the counter to all low outputs.

As presetting is synchronous, setting up a low level at the load input disables the counter and satasheet the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable input. Specify by appending the suffix letter “X” to the datsheet code. These counters are fully programmable; that is, the outputs may be preset to either level. The ripple carry output thus enabled will produce a high- level output pulse with a duration approximately equal to the high-level portion of the Q.


The input pulses are supplied by generators having the following characteristics: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The clear function for the DM74LSA is asynchro- nous; and a low level at the clear input sets all four of the flip-flop outputs LOW, regardless of the levels of dm74ls161ab, load, or enable inputs.

Fairchild Semiconductor – datasheet pdf

Clock Frequency Note 3. This mode of operation eliminates the output counting spikes which are normally associated with asynchronous ripple clock counters. Synchronous operation is pro- vided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable inputs and internal gating.

Devices also available in Tape and Reel. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Clear Release Time Note 3. The carry output is decoded by means of a NOR gate, thus preventing spikes during the normal counting mode of operation.

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