Order Number DM54LSJ, DM54LSW, DM74LSN or DM74LSWM. See Package Number J20A, M20B, N20A or W20A. March DM74LS/. DM74LSN. N20A. Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS- , ” Wide. DM74LSWM. M20B. Lead Small Outline Integrated. DM74LSN Octal D-type Transparent Latches And Edge-triggered Flip-flops DM74LS Details, datasheet, quote on part number: DM74LSN.

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When the enable is taken LOW the output will be latched at the level of the data that dm74le373n set up. The output control does not affect the internal operation of.

Datasheet Link Thanks in advance Marc. When it is high, the latch is transparent, as in, what is on the input is on the output.

Nov 22, 4. Nov 22, 2. Q outputs will be set to the logic states that were set up at.

May 19, 1, 1, Devices also available in Tape and Ddm74ls373n. A buffered output control input can be used to place the. I wasn’t driving my inputs with anything, and thus my LED’s were glowing I guess the output is high by default if there is nothing driving the input.


A buffered output control input can be used to place the eight outputs in either a normal logic state HIGH or LOW logic levels or a high-impedance state.

Help With DM74LS373N

No, create an account now. The high-impedance state and increased high-logic level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system datssheet need for inter- face or pull-up components.

When C goes low, the last state is held. The high-impedance state md74ls373n. Quote of the day. C is the latch enable. Yes, my password is: That is, the old data can be retained or new data can be entered even while the outputs are OFF.

Here’s an overview of the major players in the new RTOS world. Your name or email address: The eight flip-flops of the DM74LS are edge-triggered. They are particularly attractive. Nov 22, 1.

The output control does not affect the internal operation of the latches or flip-flops. Help with state table Posted by arcsky in forum: Do you already have an account? In the high-imped- ance state the outputs neither load nor drive the bus lines significantly. Or there is no delay time, just following the sequence of 2.


I think for what you are doing it should be tied low all the time.

Help With DM74LSN | All About Circuits

Any help would be much appreciated!! You May Also Like: Anyway, for some reason I can’t figure out how to properly latch data inputs to the LSN. OC output control enables the output drivers when it is low. Home – IC Supply – Link. Nov 22, 3. Q outputs will follow the datadheet D inputs. However I am not getting this result. Thanks guys, I figured it out. I have tried every combination of OC and g in order to see outputs matching the inputs.

On the positive transition of the clock, the Q outputs will be set to the logic states that were set up at the D inputs. Working with Fluctuating Input Supplies:

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