EC2354 VLSI DESIGN 2 MARKS WITH ANSWERS PDF

SUBJECT NAME: VLSI DESIGN. SUBJECT CODE: EC UNIT I CMOS TECHNOLOGY. PART –A (2 MARKS). 1. What are four generations of Integration. EC / EC64 VLSI Design 2 Marks With Answers ECE 6th Semester Regulation | BE Electronics and Communication Engineering. Sixth Semester. 2 MARK QUESTION AND ANSWERS. ECVLSI DESIGN is CMOS technology? Complementary Metal Oxide Semiconductor (CMOS)in which.

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E2354 is similar in syntax to the C programming language. If and when a discrepancy is detected between the faulted circuit response and the good circuit response, the fault is said to be detected and the simulation is stopped. On application of appropriate programming voltages, the antifuse is changed permanently to a low resistance structure W.

What is an antifuse? What are the categories of testing? The amount of time needed for a change in a logic input to result in a permanent change at an output that is the combinational withh will not show any further output changes in response to an input change. The Device that conduct with zero maks bias. Metastability is an unknown state it is neither zero nor one.

Define local skew, global skew, and useful skew. Verilog supports four levels for the values needed to describe hardware referred to as value sets. Define propagation delay and contamination delay? That is, the output node is always a low impedance node in steady state.

What is dynamic power dissipation? A carry skip adder consists of a simple ripple carry adder with a special speed up carry chain called a skip chain.

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What is mean by power and power dissipation? N channel transistors have greater switching speed when compared to PMOS transistors.

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No Latch Flip Flop 1. What are the steps performed to achieve lithography friendly design? What are the disadvantages of dynamic CMOS technology? Latch up is a condition in which the parasitic components give rise to the establishment of low resistance conducting paths between VDD and VSS with disastrous results.

EC – VLSI Design TWO MARKS WITH ANSWERS | Manoharan K. –

What is metastability and list the steps to prevent it? The simplest multiplier is the Braun multiplier. A ripple carry adder has a performance that is linearly proportional flsi the number of bits.

Give the classifications of timing control?

A device connected so as to pull the output voltage to the upper supply voltage usually VDD is called wth up device. The standard cell areas also called flexible blocks in a CHIC are built of rows of standard cells.

Value levels Condition in hardware circuits 0 Logic zero, false condition 1 Logic one, true condition X Unknown logic value Narks High impedance, floating state Latch up is a condition in which the parasitic components give rise to the establishment of low resistance conducting paths between VDD and VSS with disastrous results.

A single layout is used repetitively for every bit in the data word. The number of transistor is getting doubled in every 18 months based on moore’s law Higher speed of operation: Electrically Erasable Programmable Read only Memory. Because of finite delay of the gates used to realize the Boolean functions, different signals cannot reach the inputs of a gate simultaneously this leads to spurious transition at the output before it settles down to its final value, the spurious transitions leads to charging and discharging of the outputs causing glitch power dissipation.

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Needs a precharge clock. Why low power has become an important issue in the VLSI circuit realization? A device connected so as to pull the output voltage to the upper supply voltage usually VDD is called pull up device. Write notes on manufacturing tests? Write down the expression to obtain delay for N bit carry bypass adder.

What is answerx as percentage-fault coverage? What is short circuit power dissipation? In a PAL, the device is programmed by changing the characteristics if the switching element. Wafer polishing and etching 5. What is a Manjestor carry chain adder? State the different types of ,arks processes. Circuit optimizations concentrate on reducing the delay of the carry path.

Iterative logic array testing What is known as test data register? What is the structural gate-level modeling? The test-data registers are used to set the inputs of modules to be tested, and to collect the results of running tests. A fundamental difficulty with dynamic circuits is a loss of noise immunity and a serious timing restriction on the inputs of the gate. It is used to convey information through the use of color code. Channels gate array Channel less gate array Only the interconnect is 1.

A number of circuit topologies exist wigh that careful optimization of the circuit topology and the transistor sizes helps to reduce the capacitance on the carry bit 3.

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